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LOS ALTOS, Calif.--(BUSINESS WIRE)--June 11, 2001--AT DAC BOOTH #844--

Eliminates Need for External Testbench Utilities, Enabling

High-Performance, Easy-to-Use, Powerful Verification Environment

Co-Design Automation, Inc. an electronic design automation (EDA) software supplier, today announced it has added verification capabilities to its system-level simulator, eliminating the need for external testbench utilities by providing an easy-to-use, high-performance and powerful simulation/verification environment.

Additionally, Co-Design has extended its SUPERLOG® language to enable an easy-to-use mechanism for automating testbench generation.

``Our customers have reported that this breakthrough technology offers the fastest -- by a wide margin -- verification/simulation environment available today,'' notes Simon Davidmann, chief executive officer of Co-Design Automation. ``With the addition of SUPERLOG extensions to simplify the test environment, we are able to deliver dramatic productivity improvements to the market.''

``SUPERLOG has set a new direction in verification functionality that solves a number of issues present in other environments,'' remarks Harry D. Foster, senior member of the CAD Technical Staff at Hewlett-Packard Company. ``By providing powerful testbench features using a Verilog coding style, Co-Design Automation has enabled a highly effective functional test mechanism that will appeal to a broad range of design and verification engineers.''

A new simulation algorithm allows verification automation functions to be executed directly from the simulation engine, transforming the performance and usage characteristics of verification environments. Co-Design's UNIfied VERification Simulation ALgorithm (UNIVERSAL) operates by blending verification mechanisms directly into an enhanced SYSTEMSIM(TM) simulation kernel. This technique eliminates interpreted external test-generation mechanisms indirectly connected to simulation engines through the programming language interface (PLI). The result is advanced testbench automation, operating several times faster than traditional systems. In addition, simulation debug capabilities operate on both the design and testbench, simplifying the analysis of verification runs.

SYSTEMSIM now includes SUPERCHARGER, a high-performance simulation engine, as well as additions to the CBlend(TM) technology that allows Verilog hardware description language (HDL) and SUPERLOG code to be called from a C/C++ program.

Co-Design has embedded several cooperating functional test automation capabilities in SYSTEMSIM to detect complex corner case issues with a minimal number of simulation cycles and reduced testbench coding effort. Capabilities include constrained random test generation, functional test coverage, assertion and property checks, plus data manipulation and queuing functions.

The SUPERLOG language has been enhanced to support greater verification facilities, giving designers an evolutionary approach from Verilog for testbench specification, eliminating various language issues associated with other solutions. SUPERLOG adds advanced programming constructs to a Verilog base, essential to testbench creation, including C syntax and functionality, system functions such as advanced interfacing for bus functional models, and many object oriented style features.

C and C++ code may be accessed across verification environments using SYSTEMSIM's CBlend interface.

``In my opinion, the SUPERLOG language provides welcome enhancements to Verilog that encapsulate critical components for comprehensive system testbenches, while increasing designer productivity,'' notes Bob Beckwith, distinguished engineer at Mint Technology, Inc. ``Coupled with the CBlend C / SUPERLOG co-execution technology, the result is an extremely compelling tool set that leverages existing knowledge and techniques, eliminating a significant portion of the work involved in creating a verification environment.''

SYSTEMSIM will be continuously demonstrated at the 38th DAC Monday, June 18, through Wednesday, June 22, at the Las Vegas Convention Center in Booth Number 844.

Pricing and Availability

The latest version of SYSTEMSIM is shipping now and is priced at $40,000, U.S. list, for a perpetual license. The UNIVERSAL simulation algorithm and SUPERLOG verification features are available today and included as part of the simulator at no extra charge. SYSTEMSIM runs on Sun Solaris and Linux.

Contact Dave Kelf, Co-Design's vice president of marketing, for more details. He can be reached via email at davek@co-design.com or at (877) 6 CODESIGN, Ext. 404.

About Co-Design Automation

Co-Design Automation is an EDA company focused on the efficient creation, implementation, and verification of system on chip (SOC) designs. It is privately held and funded by investors from within the EDA developer and user communities. The staff includes notable simulation experts Phil Moorby, creator of the Verilog HDL and the first fellow at Cadence Design Systems, Inc. (NASDAQ: CDN), and Peter Flake, creator of the HILO HDL. In 1999, Co-Design announced the SUPERLOG(TM)system design language, now utilized by 15 partner companies. Its products -- SYSTEMSIM and SYSTEMEX -- are achieving success throughout the electronics industry worldwide in system platform and advanced verification applications. Corporate headquarters is in Los Altos, Calif. Telephone: (877) 6 CODESIGN. Facsimile: (408) 273-6025. Email: info@co-design.com. On-line information is found at its Web Sites: http://www.co-design.com and http://www.superlog.org.

SUPERLOG is a registered trademark and SYSTEMSIM, SYSTEMEX, CBlend are trademarks of Co-Design Automation, Inc. Verilog is a trademark of Cadence Design Systems, Inc. Co-Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

     Co-Design Automation, Inc.
     David Kelf
     (617) 571-9883
     davek@co-design.com
      or
     Nanette Collins
     (617) 437-1822
     nanette@nvc.com